1. Field of the Invention
The embodiments of the invention generally relate to jitter measurement, and, more particularly, to a built-in self-test (BIST) circuit for measuring phase and/or cycle-to-cycle jitter of a clock signal.
2. Description of the Related Art
Phase locked loops (commonly referred to as PLLs) are found in a large number of computer, wireless, and communication systems with many different applications such as clock recovery, frequency synthesis and clock noise filtration. In the last several decades, a rapid increase in the speeds of digital circuitry have put strenuous demands upon PLL designers. One result of the fast increase in performance is that harmful noise parameters are becoming a relatively larger design problem. One such parameter, jitter, has quickly become one of the most critical parameters in specifying the operation of a PLL. As a result, extremely accurate analysis of PLL jitter characteristics is becoming required during production testing to ensure the PLL performs within its design specifications. With clock signals getting faster each year, the ability to measure jitter in the realm of picoseconds (ps) is becoming essential. However, in high volume production of PLLs there are very few mechanisms implemented to monitor jitter. Thus, PLLs could be shipped to clients who assume the circuit is within jitter specifications, when actually no concrete information has been developed to either prove or disprove the fact.
As a result, designers have recently been looking towards built-in self-test (BIST) solutions. In a high volume production setting, BIST solutions can offer a low-cost, accurate, and fast solution in determining jitter. Thus, disclosed herein are embodiments of a BIST circuit that can determine PLL jitter with high accuracy over a wide input frequency range.